operating duty:

1. Responsible for the back-end design of CMOS Digital IC, including floorplan, timing analysis, clock tree synthesis, route, power analysis, SI analysis and other automatic layout and wiring design.

2. Participate in the layout planning of SOC chip.

3. Participate in the top-level integration of SOC chip layout.

Job requirements:

1. Bachelor degree in Microelectronics or related majors, and IC digital back-end design experience.

2. Have basic knowledge of digital circuit and analog circuit, and have knowledge of analog circuit is better.

3. Be skilled in using digital IC back-end design tools (preferably ICC).

4. Have solid time sequence convergence and signoff skills.

5. Proficient scripting skills (Perl, TCL or Python).

6. Willing to participate in the field of semiconductor chip design, pursue perfect engineering quality, strong sense of responsibility, and strong thirst for new knowledge.

7. Be able to communicate and cooperate well with designers.