operating duty:

1. Responsible for SoC IP scheme design, including spec definition, RTL coding, function simulation, lint check and CDC check;

2. Support IP integration, DFT and PR;

3. Participate in FPGA system debugging;

4. Participate in chip testing scheme and support chip testing.

Job requirements:

1. Have more than 2 years of relevant work experience, bachelor degree or above, major in electronic engineering, microelectronics, computer, communication and other related fields;

2. Have a deep understanding of ASIC design process and strong RTL design experience;

3. Strong communication and coordination skills, good team spirit;

4. The following experience is preferred: successful development of wireless communication baseband IP, deep understanding of wireless communication algorithms, including but not limited to WiFi / ble / UWB, etc.