operating duty:

1. Skillfully analyze the target to be tested and extract the verification vector;

2. Responsible for developing verification environment including module level and system level, verification script tools, and maintaining verification process;

3. Work closely with design engineers, understand module and chip design specifications, and lead other engineers to complete project verification;

4. Test platform development, direct test case and randomized test case design and function coverage generation based on high-level hardware language such as SystemVerilog;

5. Be able to cooperate with design and firmware engineers in FPGA platform verification and debugging, and apply advanced verification methods to project verification.

Job requirements:

1. Master degree or above, major in computer science or electronic engineering;

2. Experience in IC Verification;

3. Full of ambition and good team work ability;

4. Familiar with ASIC design process, have a deep understanding of UVM verification methodology;

5. Experience in SOC, deep learning, video codec or graphics and image processing module verification is preferred

6. Good communication and expression skills, able to write various work reports with high quality